ISSN 2380-4505
Vol. 2024, Issue DPC, 2024January 23, 2025 EDT
Atomic Layer Deposition + Parylene Conformal Nanocoatings for Robust Corrosion Protection of Electronics
Atomic Layer Deposition + Parylene Conformal Nanocoatings for Robust Corrosion Protection of Electronics
Articles in Vol. 2024, Issue DPC, 2024
Vol. 2024, Issue DPC, 2024
- Advanced Packaging: Enabling the Future of Moore’s LawPooda Tadayon
- Applications of White Light Interferometry in Advanced Packaging: Metrology and Quality AssuranceRavi ChintalaDaphne MariaraviSamuel Lesko
- Liquid Metal Embedded Elastomers (LMEE) as Low-BLT Thermal Interface MaterialsDylan Shah
- "Zero-Power" Additively Manufactured FHE-Enabled Wireless/5G+ Ultrabroadband Modules for IoT, Industry 4.0 and Smart Cities ApplicationsKexin HuManos M. Tentzeris
- 3.5D Packaging for Heterogeneous IntegrationChintan Buch
- Overlay Analysis and Optimization for High-Accuracy Hybrid D2W BondingPieter Bex
- 5G Electronics: Bridging the Measurement Challenges with Reference Material DevelopmentLucas EnrightM. Olszewska-PlachaM. J. HillSay PhommakesoneD. KatoC. A. HillH. Kähäri,C. LeeC. S. ChenNate OrloffM. CeluchUrmi Ray
- The Mid-Atlantic Semiconductor Hub (MASH): A Distributed Network of Resources and Talent to Reassert U.S. Leadership in Semiconductor ManufacturingDaniel Lopez
- A Novel Approach to Co-Design of Analog and RF Multi-Die PackagesJohn Park
- High-end Smartphone SoC Packaging Comparison - Advanced PoP Technology from Standard, Fan-Out to Flip-Chip AssemblyRayane MazariGabriela Pereira
- Enabling Heterogenous Integration Through Chiplet ArchitecturesHemanth Dhavaleswarapu
- Advanced Package Evaluation Platform through CollaborationHidenori Abe
- Revitalizing Domestic Semiconductor Manufacturing: Challenges, Opportunities and Emerging ApplicationsMark Litecky
- Convergence of Academic Excellence, Industry Innovation, and Government Investment to Propel Advanced Packaging at ASUZachary Holman
- CHIPS for America, National Advanced Packaging Manufacturing Program (NAPMP) and R&D UpdateDaniel Berger
- Custom, High Density Power Modules Enabled by Thermal Integration TechnologiesErrol Porter
- P-WLCSP Advanced Packaging Enabling Next Generation Medical Device ApplicationsDoug HacklerEd Prack
- Soldering Defects on Immersion Tin and the Impact of the Tin-Oxide LayerBritta SchafstellerBernhard SchachtnerKenneth LeeHubertus MertensGustavo Ramos
- Process Considerations for Defluxing Ultra-Fine Pitch Die on CoWsRavi Parthasarathy
- Heterogeneous Packaging Technologies for Chiplet and Memory IntegrationYan LiWooPoung Kim
- 2nd Generation 3D V-Cache TM EnablementArsalan AlamChandrasekhar MandalapuPatrick ChengChihHsiang TsengSean LiuLiwei WangMihaela TanasescuMahmudur ChowdhuryAly GarciaAnadi SrivastavaSai VadlamaniSireesha GogineniTanmay MudholkarJiali ORiainYash KothariYong fui LeeLitao YangAnna YangPawan KulkarniAaron BlanchetRita PillmanBryan WeatherfordTao ChenYolanda LiuRaja Swaminathan
- Chiplets and Heterogeneous IC Packaging: Building Blocks and TradeoffsMike KellyDave HinerSuresh Jayaraman
- An Innovative Deposition Technology for Conductive & Dielectric MaterialsStephane Etienne
- Discrete Carbon Nanotubes vs. Carbon Fiber: Nano-Uniform Surface Resistance for Next Gen ESD-Safe FixturesBrandon Sweeney
- Atomic Layer Deposition + Parylene Conformal Nanocoatings for Robust Corrosion Protection of ElectronicsRakesh KumarShuichi Sawada
- Novel Pressure-less Adhesive Dispensing Strategy for Thin Die ApplicationsMatteo Luca Quattrocchio
- Novel Low Loss Polymer for Advanced IC PackagingHikaru MizunoTakeru KameyamaYuutoku YamashitaKenta NishinoShintarou FujitomiNaoyuki Kawashima
- Advances in Vertical Wire Bonding Enable Low-Cost Shielding and Wafer Level Interconnect SolutionsJohn Foley
- Metrology of Electrodeposition of New Iron-alloy Barrier Layers in PackagingPatrick SaittaJingjing WangEugene Shalyt
- Annealing Behavior of Electroplated Nano-grained CopperTsvetina DobrovolskaMartin MackKlaus LeyendeckerYun ZhangPeipei DongKevin Martin
- New Innovative Way to Verify Package ConnectivityJustin LockeMike WalshJin Hou
- Improved Yield Estimation for Heterogeneously Integrated ComponentsAndrew FerrisMatthew Jordan
- Saras Embedded STile TM IPD Technology for High Performance Power Delivery NetworksBart DeProspo
- Advanced Mechanical Analysis Workflow for Chiplets Integration Predictive DesignLihong CaoChinli KouChen-Chao WangChieh Lo
- Thin Glass Interposers with High-Density InterconnectsShelby F. Nelson
- Achieving Large-Scale HBM Integration with Adaptive Pad Stacks on Molded Embedded Bridge Die InterposersBenedict San JoseCliff SandstromCraig BishopTim Olson
- Multi-axis Process integration for Wafer Scale and Substrate-Like Printed ElectronicsC. Mike NewtonRudy GhoshGrant WachtelConnor Whitley
- Aerosol Jet Printing for Three Dimensional InterconnectsMichael Renn
- Die-First FOPLP Lithography Challenges Due To Die Shifting And A Solution Using Feedforward Adaptive Shot TechnologyJohn ChangJian LuTimothy ChangKeith Best
- Scalable Core Package for Power Module with Double-Sided Cooling Capability Applying Fan-out Panel-Level Process Suitable for SiC and GaNKatsuhiro TakaoAtsushi KurohaMichihito KawadaIchiro KonoTakashi SuzukiYoshiaki Aizawa
- Patterning Fine Pitch L/S on Photosensitive PBO Using Laser Direct Imaging for High-Density Interconnect ApplicationsSiyang LiuMayukh NandyYanze WuHongbin Yu
- Novel Low Warpage Mold Film for FO WLP/PLP ApplicationMeiten Koh
- A Study of Low Temperature Solder on Microstructure and ReliabilityAllen XuNokibul IslamJoe LiuXiaojing MuYaojian LinDanfeng Yang
- Cold Sprayed Copper-Diamond Composites for Thermal Management of Semiconductor PackagesWenhao (Eric) LiFeras EidYoshihiro TomitaJohanna Swan
- Exploring the Engineering of Copper Grains to Electroplate Bamboo-Like Structures and Foster Cu (111) Oriented Films in Pursuit of Enhanced Device ReliabilityAbdelhamid El-Sawy
- A Novel, Automated Measurement and Analysis Technique forBonding Energy of Fusion and Hybrid Wafer to Wafer BondingAndrew TuchmanSatohiko HoshinoAdam GildeaChristopher NetzbandIlseok Son
- 5G/6G Roadmap Creation and Packaging ChallengesUrmi Ray
- Delivering the Full Benefits of Maskless Lithography and Adaptive Patterning with Comprehensive Design AutomationGaurang Gunde
- Materials-Technology Co-Optimization (MTCO) for Inter-Die-Gap-Fill (IDGF) in Heterogeneous Integration of ChipletsSean SeutterZongbin WangLulu XiongPeng LuoZijie HongDoug LeeBalamurugan RamasamyPeng SuoPrayudi LiantoGuan Huei See
- Application of Picosecond Acoustic Metrology for monitoring Metal Films in Advanced PackagingM. MehendaleK. ParkY. T. HanJ. DaiC. KimG. A. AntonelliP. Mukundhan
- Reliable Direct Bonded Heterogeneous Integration (DBHi) for AI HardwareDivya TanejaKatherine PilgerAlexis Jacques-FortinMaxime GodardIsabel de SousaSayuri KoharaChinami MarushimaTakahito WatanabeAkihiro HoribeJoseph RossThomas Wassick
- High Density Organic Substrates for Chiplet TechnologiesLars Böttcher
- Meeting the Explosive Demands of AI with Chiplet ArchitecturesArvind Kumar
Kumar, Rakesh, and Shuichi Sawada. 2025. “Atomic Layer Deposition + Parylene Conformal Nanocoatings for Robust Corrosion Protection of Electronics.” IMAPSource Proceedings 2024 (DPC): 834–61. https://doi.org/10.4071/001c.129018.