ISSN 2380-4505
Vol. 2021, Issue HiTEC, CICMT, Power, 2021April 01, 2021 EDT
Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits
Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits
Philip G. Neudeck, David J. Spry, Michael J. Krasowski, Liangyu Chen, Lawrence C. Greer, Carl W. Chang, Dorothy Lukco, Glenn M. Beheim, Norman F. Prokop,
Articles in Vol. 2021, Issue HiTEC, CICMT, Power, 2021
Vol. 2021, Issue HiTEC, CICMT, Power, 2021
- Novel Materials and Structures for Wide and Ultra-Wide Bandgap Semiconductor SwitchesA. Christou
- 4–20mA optical sensor at 300C using SiC and SOI integrated circuitsCheng-Po ChenEmad Andarawis
- 300°C Optical CommunicationsEmad AndarawisCheng-Po (Paul) ChenBaokai Cheng
- A High Temperature SOI-CMOS Chipset Focusing Sensor Electronics for Operating Temperatures up to 300 °CHolger KappertSebastian BraunNorbert KordasAndre KosfeldAlexander UtzConstanze WeberOlaf RämerMalte SpanierMartin IhleSteffen ZiescheRainer Kokozinski
- Effect of High Temperature Storage on AC Characteristics of Polymer Tantalum CapacitorsAlexander Teverovsky
- Bridging the Gap: A Qualitative Study on the Viability and Performance of Metalized Polyetherimide (PEI) Film Capacitors at High TemperatureDaniel TylerSvetlana LukichRaul DePersiaChase GuilbeauMark Carter
- GE SiC Semiconductor Device Operation at Extreme TemperaturesDavid Esler
- Enhancement Mode GaN-FETs in Extreme Temperature Conditions, Part I: Static Parasitic ParametersMartijn S. DuraijYudi XiaoGabriel ZsurzsanZhe Zang
- Enhancement Mode GaN-FETs in Extreme Temperature Conditions, Part II: Dynamic Parasitic ParametersMartijn S. DuraijYudi XiaoGabriel ZsurzsanZhe Zang
- Package Design and Analysis for Vertical Gallium Nitride Field Effect TransistorsJohn HarrisDavid HuitinkDan Ewing
- Upscaling of 500 °C Durable SiC JFET-R Integrated CircuitsPhilip G. NeudeckDavid J. SpryMichael J. KrasowskiLiangyu ChenLawrence C. GreerCarl W. ChangDorothy LukcoGlenn M. BeheimNorman F. Prokop
- A 96% Alumina based Packaging System for 500°C Test of SiC Integrated CircuitsLiangyu ChenPhilip G. NeudeckDavid J. SpryGlenn M. BeheimGary W. Hunter
- Alternative Setup for Long-Duration Low-Duty-Cycle 600°C Ambient Testing of SiC Integrated CircuitsAlain IzadnegahdarStephanie L. BoothDavid J. SpryPhilip G. Neudeck
- 470 Celsius Packaging System for Silicon Carbide ElectronicsN. ChiolinoA. M. FrancisJ. HolmesM. BarlowC. Perkowski
- Simulating the Effect of Rigid Frameworks on the Mechanical Properties of Transient Liquid Phase Sintered (TLPS) AlloysGilad NavePatrick McCluskey
- A 300°C High Reliability HALT/HAST Screening/Sorting Procedure for Ceramic Capacitors – Part 2Harold L. Snyder
- Designs for reliability and failure mode prevention of electrical feedthroughs in integrated downhole logging toolsHua XiaNelson SettlesMichael GrimmGaery RutherfordDavid DeWire
- Low Loss LTCC Ag System for 5G ApplicationsEllen TormeyChao MaJohn MaloneyBradford SmithSid SridharanYi Yang
- Smart Ultrasonic Welding – A Versatile Interconnection Technology for Power Electronics PackagingMatthias HunstigSebastian HoltkämperLars HelmichMichael Brökelmann
- Silicon Carbide Junction Field Effect Transistor Compact Model for Extreme Environment Integrated Circuit DesignS. PerezA.M. FrancisJ. HolmesT. Vrotsos
Neudeck, Philip G., David J. Spry, Michael J. Krasowski, Liangyu Chen, Lawrence C. Greer, Carl W. Chang, Dorothy Lukco, Glenn M. Beheim, and Norman F. Prokop. 2021. “Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits.” IMAPSource Proceedings 2021 (HiTEC, CICMT, Power): 64–68. https://doi.org/10.4071/2380-4491.2021.HiTEC.000064.