ISSN 2380-4505
Vol. 2016, Issue S2, 2016October 01, 2016 EDT
Chip Package Interaction Considerations in Fan-out Wafer Level Packaging
Chip Package Interaction Considerations in Fan-out Wafer Level Packaging
Articles in Vol. 2016, Issue S2, 2016
Vol. 2016, Issue S2, 2016
- On the Way from Fan-out Wafer to Fan-out Panel Level PackagingKarl-Friedrich BeckerTanja BraunS. RaatzM. MinkusV. BaderJ. BauerR. AschenbrennerR. KahleL. GeorgiS. VogesM. WöhrmannK.-D. Lang
- FO-WLP: A Disruptive TechnologyJan Vardaman
- Experimental Study on 28nm Chip/Package Interactions in eWLB (Embedded Wafer Level BGA) Fan-Out Wafer Level PackagesDongkai ShangguanYao Jian LinWon Kyung ChoiSeng Guan ChowSeung Wook Yoon
- FOWLP Technology eWLB - Enabler for Packaging of IoT/IoE ModulesSteffen Kroenhert
- Chip Package Interaction Considerations in Fan-out Wafer Level PackagingUrmi Ray
- Assessment of Optimized Process Quality and Reliability for Wafer Level ApplicationsEnnis OgawaAimin XingDavid F.-S. LiaoTen V. Y. TenChong Wei NeoFeynman W.-C. ChiangGaius SeeMabrouk ChaaraGeorge HungEndruw JahjaSteven NguyenMichael HsiehRicky W. M. ChenDarren M.-L. HoSusan R. MulfordHugh Jorge-EstevezMelissa LauLeah HilbornKashish ShahRichard MahJeff MendozaBei ZhuGalen KirkpatrickYing-Ying HsiehPaolo SamsonJames S. J. TongLiming TsauJ.K. WangVijay ReddyFrank HuiJaved SandhuManoj NairKeith TanEdward Law
Ray, Urmi. 2016. “Chip Package Interaction Considerations in Fan-out Wafer Level Packaging.” IMAPSource Proceedings 2016 (S2): S1–13. https://doi.org/10.4071/isom-2016-slide-7.