Fine Line and Low Stress RDL Solition for Fan-Out Wafer Level & Panel Level Packaging

Yoshinori Matsuura; Tatsuya Yoshida; Yukiko Komiya; Toshimi Nakamura; Takenori Yanai; Kazuhiro Okuyama; Yukiko Kitabatake; Rintaro Ishii; Katsuyuki Hayashi; Takashi Kubota; Joji Fujii

doi:10.4071/1085-8024-2021.1.000039

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Vol. 2021, Issue 1, 2021

October 01, 2021 EDT

Fine Line and Low Stress RDL Solition for Fan-Out Wafer Level & Panel Level Packaging

Yoshinori Matsuura, Tatsuya Yoshida, Yukiko Komiya, Toshimi Nakamura, Takenori Yanai, Kazuhiro Okuyama, Yukiko Kitabatake, Rintaro Ishii, Katsuyuki Hayashi, Takashi Kubota, Joji Fujii,

Carrier technology HRDP® (High Resolution Debondable Panel) Mechanical debond Line/Space (L/S) Chip Last RDL Fan-Out Wafer Level (FO-WLP) Panel Level Package (PLP) Coefficient of thermal expansion (CTE)

• https://doi.org/10.4071/1085-8024-2021.1.000039

IMAPSource Conference Papers

Matsuura, Yoshinori, Tatsuya Yoshida, Yukiko Komiya, Toshimi Nakamura, Takenori Yanai, Kazuhiro Okuyama, Yukiko Kitabatake, et al. 2021. “Fine Line and Low Stress RDL Solition for Fan-Out Wafer Level & Panel Level Packaging.” IMAPSource Proceedings 2021 (1): 39–44. https://doi.org/10.4071/1085-8024-2021.1.000039.

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