ISSN 2380-4505
Vol. 2018, Issue HiTEC, 2018May 01, 2018 EDT
Modelling the Influence of Conformal Coatings on Thermo-Mechanical Fatigue of Solder Interconnects in Electronic Packages
Modelling the Influence of Conformal Coatings on Thermo-Mechanical Fatigue of Solder Interconnects in Electronic Packages
Maxim Serebreni, Ross Wilcoxon, F. Patrick McCluskey,
Articles in Vol. 2018, Issue HiTEC, 2018
Vol. 2018, Issue HiTEC, 2018
- Environmentally Hardening IC Die Previously Assembled in Plastic Packages through Die Removal, Bond Pad Replating and Reassembly into Hermetic PackagesCharlie BeeboutErick M. Spory
- Influence of Initial Shear Strength on Time-to-Failure of Copper (Cu) Wire Bonds in Thermal Aging ConditionSubramani ManoharanChandradip PatelStevan HunterPatrick McCluskey
- Monitoring Magma Under Volcanoes: The Future Of Eruption Forecasting And Geothermal EnergyJohn Eichelberger
- Highly Reliable Pressure-Less Silver Sintering JointsSihai ChenWilliam ShambachChristine LaBarberaNing-Cheng Lee
- Mitigation of High Temperature Environments on Electrical DisconnectsKenneth P. Dowhower
- Organic Hybrids for Circuit Assemblies – Initial environmental testing of a low cost alternative to ceramic substrate based assembliesMartin WickhamKate ClaytonAna RobadorChristine Thorogood
- Identification of thermo-mechanical fatigue fracture location by transient thermal analysis for high-temperature operating SiC power module assembled with ZnAl eutectic solderFumiki KatoHiroki TakahashiHidekazu TanisawaKenichi KouiShinji SatoYoshinori MurakamiHiroshi NakagawaHiroshi YamaguchiHiroshi Sato
- New Capacitance Sensor PerformanceDavid Andrew
- US Geothermal Funding Outlook (Reducing Cost Barriers for HT SOI Reservoir Monitoring Systems)Randy A. Normann
- Digital Logic Synthesis for 470 Celsius Silicon Carbide ElectronicsN. ChiolinoA. M. FrancisJ. HolmesM. Barlow
- From Chips to Modules: Tackling the High Temperature Design ChallengePierre DelatteZlatan Gradincic
- Co-optimized Reliability and Parasitic inductance in Small Footprint Vertical Silicon Carbide MOSFETM. MontazeriS. SealA. WallaceA. MantoothD. Huitink
- Sixty Earth-Days Test of a Prototype Pt/HTCC Alumina Package in Simulated Venus EnvironmentLiangyu ChenPhilip G. NeudeckRoger D. MeredithDorothy LukcoDavid J. SpryLeah M. NakleyKyle G. PhillipsGlenn M. BeheimGary W. Hunter
- Conductive Fusion Technology Advanced Die Attach Materials for High Power ApplicationsMaciej PatelkaNicholas KrascoSho IkedaToshiyuki SatoMiguel GoniElbara ZiadeAaron J. Schmidt
- Yearlong 500 °C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated CircuitsPhilip G. NeudeckDavid J. SpryMichael J. KrasowskiNorman F. ProkopGlenn M. BeheimLiang-Yu ChenCarl W. Chang
- Robust Reliability of Ceramic Capacitors for Power ElectronicsAbhijit GuravJohn BultitudeJohn McConnellReggie Phillips
- A 300°C High Reliability HALT/HAST Screening/Sorting Procedure for Ceramic CapacitorsHarold L. Snyder
- Configurable Digital Logic for Extreme EnvironmentsRichard Rea
- High heat-density SiC heater chip for thermal characterization of high temperature packagingNaoki WakasugiShijo NagaoKim DongjinKatsuaki Suganuma
- Analog and Logic High Temperature Integrated Circuits Based on Enhancement Mode Planar SiC JFETsPeter AlexandrovMatt O'GradyNeil MerrettLaura Walter
- Novel solder-mesh interconnection design for power module applicationsAdrian LisHiroaki TatsumiTomoki MatsudaTomokazu SanoYoshihiro KashibaAkio Hirose
- Lifetime and Failure Modes of High Temperature SOI ProductsDerek MaxwellMarshall SoaresMatt Coreless
- Performance Test Results of a Precision Data Acquisition and Control Platform for 200°C+ High Temperature EnvironmentsJeff WatsonMaithil PachchigarRoss BannatyneClay MerrittChristopher ConradGlenn SmollingerEarle Drack
- Modelling the Influence of Conformal Coatings on Thermo-Mechanical Fatigue of Solder Interconnects in Electronic PackagesMaxim SerebreniRoss WilcoxonF. Patrick McCluskey
Serebreni, Maxim, Ross Wilcoxon, and F. Patrick McCluskey. 2018. “Modelling the Influence of Conformal Coatings on Thermo-Mechanical Fatigue of Solder Interconnects in Electronic Packages.” IMAPSource Proceedings 2018 (HiTEC): 7–14. https://doi.org/10.4071/2380-4491-2018-HiTEN-000007.