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High Temperature Conference Papers
Vol. 2018, Issue HiTEC, 2018May 01, 2018 EDT

Analog and Logic High Temperature Integrated Circuits Based on Enhancement Mode Planar SiC JFETs

Peter Alexandrov, Matt O'Grady, Neil Merrett, Laura Walter,
SiCIntegrated CircuitJFETHigh Temperature
https://doi.org/10.4071/2380-4491-2018-HiTEN-000079
IMAPSource Conference Papers
Alexandrov, Peter, Matt O’Grady, Neil Merrett, and Laura Walter. 2018. “Analog and Logic High Temperature Integrated Circuits Based on Enhancement Mode Planar SiC JFETs.” IMAPSource Proceedings 2018 (HiTEC): 79–85. https:/​/​doi.org/​10.4071/​2380-4491-2018-HiTEN-000079.
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