Analog and Logic High Temperature Integrated Circuits Based on Enhancement Mode Planar SiC JFETs

Peter Alexandrov; Matt O'Grady; Neil Merrett; Laura Walter

doi:10.4071/2380-4491-2018-HiTEN-000079

Loading [Contrib]/a11y/accessibility-menu.js

Alexandrov, Peter, Matt O’Grady, Neil Merrett, and Laura Walter. 2018. “Analog and Logic High Temperature Integrated Circuits Based on Enhancement Mode Planar SiC JFETs.” IMAPSource Proceedings 2018 (HiTEC): 79–85. https://doi.org/10.4071/2380-4491-2018-HiTEN-000079.

View more stats