Vol. 2018, Issue HiTEC, 2018May 01, 2018 EDT
Co-optimized Reliability and Parasitic inductance in Small Footprint Vertical Silicon Carbide MOSFET
Co-optimized Reliability and Parasitic inductance in Small Footprint Vertical Silicon Carbide MOSFET
M. Montazeri, S. Seal, A. Wallace, A. Mantooth, D. Huitink,
Montazeri, M., S. Seal, A. Wallace, A. Mantooth, and D. Huitink. 2018. “Co-Optimized Reliability and Parasitic Inductance in Small Footprint Vertical Silicon Carbide MOSFET.” IMAPSource Proceedings 2018 (HiTEC): 87–92. https://doi.org/10.4071/2380-4491-2018-HiTEN-000087.