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Symposium Proceedings
Vol. 2012, Issue 1, 2012January 01, 2012 EDT

Stacked Chip Thermal Model Validation using Thermal Test Chips

Thomas Tarter, Bernie Siegal,
TJ junction temperatureTJMAX maximum junction temperatureTA ambient temperature°CTR reference temperature°C or KPD power dissipationWΘJA thermal resistancejunction to ambient°C/WKF K factor°C/mVk thermal conductivityW/mKh convection heat transfer coefficientW/m2KWB wire bondFC flip-chipTTC thermal test chipIM measurement currentAVM measurement voltageVIH heating currentAVH heating voltageVBGA ball-grid-arrayPCB printed circuit boardTTB thermal test board
https://doi.org/10.4071/isom-2012-WP35
IMAPSource Conference Papers
Tarter, Thomas, and Bernie Siegal. 2012. “Stacked Chip Thermal Model Validation Using Thermal Test Chips.” IMAPSource Proceedings 2012 (1): 873–81. https:/​/​doi.org/​10.4071/​isom-2012-WP35.
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