Vol. 2012, Issue 1, 2012January 01, 2012 EDT
Stacked Chip Thermal Model Validation using Thermal Test Chips
Stacked Chip Thermal Model Validation using Thermal Test Chips
TJ junction temperature TJMAX maximum junction temperature TA ambient temperature °C TR reference temperature °C or K PD power dissipation W ΘJA thermal resistance junction to ambient °C/W KF K factor °C/mV k thermal conductivity W/mK h convection heat transfer coefficient W/m2K WB wire bond FC flip-chip TTC thermal test chip IM measurement current A VM measurement voltage V IH heating current A VH heating voltage V BGA ball-grid-array PCB printed circuit board TTB thermal test board
Tarter, Thomas, and Bernie Siegal. 2012. “Stacked Chip Thermal Model Validation Using Thermal Test Chips.” IMAPSource Proceedings 2012 (1): 873–81. https://doi.org/10.4071/isom-2012-WP35.
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