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Symposium Proceedings
Vol. 2019, Issue 1, 2019October 01, 2019 EDT

Development of Backside Buried Metal Layer Technology for 3D-ICs

Naoya Watanabe, Yuuki Araga, Haruo Shimamoto, Katsuya Kikuchi, Makoto Nagata,
three-dimensional integrated circuit (3D-IC)backside buried metal (BBM)layerthrough silicon via (TSV)power delivery network
https://doi.org/10.4071/2380-4505-2019.1.000268
IMAPSource Conference Papers
Watanabe, Naoya, Yuuki Araga, Haruo Shimamoto, Katsuya Kikuchi, and Makoto Nagata. 2019. “Development of Backside Buried Metal Layer Technology for 3D-ICs.” IMAPSource Proceedings 2019 (1): 268–73. https:/​/​doi.org/​10.4071/​2380-4505-2019.1.000268.
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