Vol. 2011, Issue 1, 2011January 01, 2011 EDT
Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration
Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration
Chien-Ying Wu, Shang-Chun Chen, Pei-Jer Tzeng, John H. Lau, Yi-Feng Hsu, Jui-Chin Chen, Yu-Chen Hsin, Chien-Chou Chen, Shang-Hung Shen, Cha-Hsin Lin, Tzu-Kun Ku, Ming-Jer Kao,
Wu, Chien-Ying, Shang-Chun Chen, Pei-Jer Tzeng, John H. Lau, Yi-Feng Hsu, Jui-Chin Chen, Yu-Chen Hsin, et al. 2011. “Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration.” IMAPSource Proceedings 2011 (1): 1–7. https://doi.org/10.4071/isom-2011-TA1-Paper1.
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