Chip Design of an 1 V RF Receiver Front-End for 5.8-GHz DSRC Applications

Jhin-Fang Huang; Wen Cheng Lai; Yong-Jhen Jiangn

doi:10.4071/isom-2013-THP21

Loading [Contrib]/a11y/accessibility-menu.js

Huang, Jhin-Fang, Wen Cheng Lai, and Yong-Jhen Jiangn. 2013. “Chip Design of an 1 V RF Receiver Front-End for 5.8-GHz DSRC Applications.” IMAPSource Proceedings 2013 (1): 820–24. https://doi.org/10.4071/isom-2013-THP21.

View more stats