Vol. 2013, Issue 1, 2013January 01, 2013 EDT
Chip Design of an 1 V RF Receiver Front-End for 5.8-GHz DSRC Applications
Chip Design of an 1 V RF Receiver Front-End for 5.8-GHz DSRC Applications
Huang, Jhin-Fang, Wen Cheng Lai, and Yong-Jhen Jiangn. 2013. “Chip Design of an 1 V RF Receiver Front-End for 5.8-GHz DSRC Applications.” IMAPSource Proceedings 2013 (1): 820–24. https://doi.org/10.4071/isom-2013-THP21.